The principles of the present invention have application to various types of non-volatile memories, those currently existing and those contemplated to use new technology being developed. Implementations of the present invention, however, are described with respect to a flash electrically erasable and programmable read-only memory (EEPROM), wherein the storage elements are floating gates, as exemplary.
It is common in current commercial products for each floating gate storage element of a flash EEPROM array to store a single bit of data by operating in a binary mode, where two ranges of threshold levels of the floating gate transistors are defined as storage levels. The threshold levels of a floating gate transistor correspond to ranges of charge levels stored on their floating gates. In addition to shrinking the size of the memory arrays, the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each floating gate transistor. This is accomplished by defining more than two threshold levels as storage states for each floating gate transistor, four such states (2 bits of data per floating gate storage element) now being included in commercial products. More storage states, such as 16 states per storage element, are contemplated. Each floating gate memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another.
As the number of states stored in each memory cell increases, the tolerance of any shifts in the programmed charge level on the floating gate storage elements decreases. Since the ranges of charge designated for each storage state must necessarily be made narrower and placed closer together as the number of states stored on each memory cell storage element increases, the programming must be performed with an increased degree of precision and the extent of any post-programming shifts in the stored charge levels that can be tolerated, either actual or apparent shifts, is reduced. Actual shifts in the charge stored in one cell can be disturbed when reading, programming and erasing other cells that have some degree of electrical coupling with that cell, such as those in the same column or row, and those sharing a line or node.
Apparent shifts in the stored charge occur because of field coupling between storage elements. The degree of this coupling is necessarily increasing as the sizes of memory cell arrays are being decreased and as the result of improvements of integrated circuit manufacturing techniques. The problem occurs most pronouncedly between two sets of adjacent cells that have been programmed at different times. One set of cells is programmed to add a level of charge to their floating gates that corresponds to one set of data. After the second set of cells is programmed with a second set of data, the charge levels read from the floating gates of the first set of cells often appear to be different than programmed because of the effect of the charge on the second set of floating gates being coupled with the first. This is described in U.S. Pat. Nos. 5,867,429 and 5,930,167, which patents are incorporated herein in their entirety by this reference. These patents describe either physically isolating the two sets of floating gates from each other, or taking into account the effect of the charge on the second set of floating gates when reading that of the first. Further, U.S. Pat. No. 5,930,167 describes methods of selectively programming portions of a multi-state memory as cache memory, in only two states or with a reduced margin, in order to shorten the time necessary to initially program the data. This data is later read and re-programmed into the memory in more than two states, or with an increased margin.
This effect is present in various types of flash EEPROM cell arrays. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, and 6,151,248, and Ser. Nos. 09/505,555, filed Feb. 17, 2000, and Ser. No. 09/667,344, filed Sep. 22, 2000.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patents that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935. Briefly, two bits of data, often from different logical pages of incoming data are programmed into one of four states of the individual cells in two steps, first programming a cell into one state according to one bit of data and then, if the data makes it necessary, re-programming that cell into another one of its states according to the second bit of incoming data.
As described in these patents, a common technique for encoding the data stored in these multi-state (or MLC) memories is to both store an upper page of data and a lower page of data in the same set of multi-level cells. This arrangement has the shortcoming, that if a physical page of MLC flash memory is being programmed with the lower page data, the user (controller) has to wait until the programming is finished to be able to start programming the upper page data, when, in fact, both the lower and upper page data are going to be programmed into the same physical page. It is also common in these designs to write data in a page containing an amount of data corresponding to multiple units of data transfer. This results in the shortcoming that if a flash memory is being partially programmed, as when a multi-sector or multi-plane page is programmed with, say, only a single sector of data, the user (controller) has to wait until programming is finished to be able to start another partial program of the same page. The performance of non-volatile memory systems could be improved if these shortcomings could be reduced or eliminated.